1. Field of the Invention
The present invention relates to a current mirror circuit, more particularly to a current mirror circuit suitable for constructing a current mirror circuit using a Bi-CMOS process, which allows mounting CMOS transistors and bi-polar (BIP) transistors on a same semiconductor integrated circuit.
2. Description of the Related Art
A current mirror circuit, which is constructed using a bi-polar (BIP) process, has been widely used for electronic circuits to implement various functions, since the output current, which is in proportion to the input current at a predetermined ratio, can be acquired in a small area at high precision. FIG. 5 shows an example of a current mirror circuit (e.g. Japanese Patent Application Laid-Open No. H06-112740). This current mirror circuit 101, where the input current I0 is input to an input terminal IN, and the output currents I1 and I2 are output to two output terminals, OUT1 and OUT2, is comprised of four NPN type BIP transistors. Specifically, for both the input side BIP transistor 110, of which collector is connected to the input terminal IN, and the output side BIP transistors 111 and 112, of which collectors are connected to the two output terminals OUT1 and OUT2, the respective emitter is grounded and a base is commonly connected. For the BIP transistor for supplying base current 113, of which the collector is connected to the power supply VCC, the emitter is connected to the base of the input side and the output side BIP transistors 110, 111 and 112, and the base is connected to the input terminal IN. In this case, the sizes of the output side BIP transistors 111 and 112 are set to be a predetermined scale factor respectively compared with the input side BIP transistor 110, so that the required output currents I1 and I2 can be acquired respectively. In this current mirror circuit 101, current branching from the input current I0 becomes the base current of the BIP transistor for supplying base current 113, and current, when this base current is amplified with the emitter ground amplification factor (hFE), becomes the total current IB of the base currents IB0, IB1 and IB2 of the input side and output side BIP transistors 110, 111 and 112. Therefore current branching from the input current I0, for the base current of the input side and output side BIP transistors 110, 111 and 112, can be small, which can decrease errors in the consistency (ratio) of the input current I0 and the output currents I1 and I2.
FIG. 6 shows an example of another current mirror circuit (e.g. Japanese Patent Application Laid-Open No. H07-231229). In the current mirror circuit 102, just like the above mentioned prior art, emitters of the input side and output side BIP transistors 110, 111 and 112 are all grounded and the bases thereof are commonly connected. Each of these bases, in this case, is connected to the collector of the output side BIP transistor 111. And the emitters of the input side and output side BIP transistors 114, 115 and 116 are connected to the collectors of the BIP transistors 110, 111 and 112 respectively, and collectors thereof are connected to the input terminal IN and the output terminals OUT1 and OUT2 respectively, and the bases are commonly connected and are also connected to the input terminal IN. This current mirror circuit 102 can fix the collectors of the BIP transistors 110, 111 and 112 to roughly the same potential (that is base potentials of these). The influence of the dependency of the BIP transistors 110, 111 and 112 on the collector potential, that is the influence of Early effect, can be controlled, which can decrease the errors in consistency (ratio) of the input current I0 and output currents I1 and I2.